A 3-disjoint path design of non-blocking shuffle exchange network by extra port alignment

• Published in: The Journal of supercomputing Vol. 78; no. 12; pp. 14381 - 14401
• Main Authors: Ansari, Abdul Q., Sharma, Vipin, Mishra, Rajesh
• Format: Journal Article
• Language: English
• Published: New York Springer US 01.08.2022; Springer Nature B.V
• Subjects: Compilers; Computer architecture; Computer Science; Converters; Data transmission; Exchanging; Fault tolerance; Interpreters; Network reliability; Network topologies; Parallel processing; Permutations; Processor Architectures; Programming Languages; Routing (telecommunications); Switches; Switching; Tags; Waveguides; Disjoint nodes and permutations; Cross bar switch; Multistage interconnection networks (MINs); Shuffle–exchange network (SEN); Reliability; Fault-tolerant
• DOI: 10.1007/s11227-022-04450-2
• ISSN: 0920-8542

Multistage Interconnection Networks (MINs) are designed to provide efficient communication via switching. These kinds of MINs are available for large-scale parallel processing. One of such kinds of MINs is Shuffle-Exchange Network (SEN), which facilitates a high level of data transmission with a number of processors working together. Designing this SEN architecture requires a different kind of switching and has wide applications in different kinds of interconnection networks such as omega, cube and binary. Previously, many topologies such as Arrayed Waveguide Gratings and tuneable Wavelength Converters have been presented, but these methods faced low reliability and fewer path possibilities. In these topologies, the connections were made backtracking and non-blocking. These connections are found to be low reliability and with improper control structures. In order to overcome these issues in the design, this paper proposed an enhanced SEN architecture using crossbar switches with five input and output ports that enabled overall path possibilities, thus improving network reliability. Path connections were done using shuffle exchange connections and permutations over source tags that are fault-tolerant. Similarly, a routing table has been implemented to optimise path selection and make the system non-blocking with less switch failure. A tag-based routing has been enabled to generate this routing table, and these tag bits are control lines of the path. There remain three disjoint paths in this routing. Routing has been done using these tags and implemented in enhanced SEN architecture, and the performance has been analysed.