Optimized Message Passing Schedules for LDPC Decoding

• Published in: Conference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers, 2005 pp. 591 - 595
• Main Authors: Radosavljevic, P., de Baynast, A., Cavallaro, J.R.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2005
• Subjects: Acceleration; Algorithm design and analysis; Belief propagation; Convergence; Error analysis; Iterative decoding; Message passing; Parity check codes; Scheduling algorithm; Turbo codes
• DOI: 10.1109/ACSSC.2005.1599818
• ISBN: 9781424401314; 1424401313
• ISSN: 1058-6393

The major drawback of the LDPC codes versus the turbo-codes is their comparative low convergence speed: 25-30 iterations vs. 8-10 iterations for turbo-codes. Recently, Hocevar showed by simulations that the convergence rate of the LDPC decoder can be accelerated by exploiting a `turbo-scheduling' applied on the bit-node messages (rows of the parity check matrix). In this paper, we show analytically that the convergence rate for this type of scheduling is about two times increased for most of the regular LDPC codes. Second we prove that `turbo-scheduling' applied on the rows of the parity check matrix is identical belief propagation algorithm as standard message passing algorithm. Furthermore, we propose two new message passing schedules: 1) a turbo-scheduling is applied on the check-node messages (columns of the parity check matrix); and 2) a hybrid version of both previous schedules where the turbo-effect is applied on both check-nodes and bit-nodes. Frame error rate simulations validate the effectiveness of the proposed schedules