Features of Dataflow Processor Emulator Implementing

• Published in: Lobachevskii journal of mathematics Vol. 41; no. 12; pp. 2614 - 2620
• Main Authors: Shabanov, B. M., Kuznetsova, E. A., Rybakov, A. A.
• Format: Journal Article
• Language: English
• Published: Moscow Pleiades Publishing 01.12.2020; Springer Nature B.V
• Subjects: Algebra; Analysis; Associative memory; Computer architecture; Data search; Data storage; Emulators; Geometry; Logic; Mathematical Logic and Foundations; Mathematics; Mathematics and Statistics; Microprocessors; Probability Theory and Stochastic Processes; Processors; dataflow graph; control flow graph; dataflow processor emulator; def-use graph; token state; associative token memory; token
• ISSN: 1995-0802; 1818-9962
• DOI: 10.1134/S1995080220120379

The development of dataflow processor architecture is a promising direction for improving the performance of computing systems. The dataflow processors have several advantages in contrast with the von Neumann architecture processors. These advantages are express in explicit parallelism of calculations, since in the presentation of programs for the dataflow processors the execution of instructions is limited solely by the fact of input data’s ready state. The concept of using tokens as data storage for instructions allows you to remove many problems associated with data conflicts and simplifies the program logic. One of the most important elements in the implementation of the logic of the dataflow processor is the associative token memory, which should provide storage and quick search for ready-made data for instructions that can be transferred for execution. This article discusses the functionality of the dataflow processor emulator and its parts including associative token memory and the logic of its operation using the example of a simple dataflow graph.