OPTIMIZED REVERSIBLE ARITHMETIC LOGIC UNITS

• Published in: Journal of electronics (China) Vol. 31; no. 5; pp. 394 - 405
• Main Authors: Moallem, Payman, Ehsanpour, Maryam, Bolhasani, Ali, Montazeri, Mehrdad
• Format: Journal Article
• Language: English
• Published: Heidelberg Science Press 18.10.2014; Department of Electrical Engineering, University of Isfahan, Isfahan, Iran%Department of Computer, Falavarjan Branch, Islamic Azad University, Falavarjan, Iran%Department of Computer, Arak Branch, Islamic Azad University, Arak, Iran%Department of Computer, Faculty of Engineering, Polytechnic University of Turin, Turin, Italy
• Subjects: Electrical Engineering; Engineering; Control unit; TN47; Full Adder (FA); Reversible Arithmetic Logic Unit (ALU); Reversible logic gates
• ISSN: 0217-9822; 1993-0615
• DOI: 10.1007/s11767-014-4081-y

Arithmetic Logic Unit （ALU） as one of the main parts of any computing hardware plays an important role in digital computers. In quantum computers which can be realized by reversible logics and circuits, reversible ALUs should be designed. In this paper, we proposed three different designs for reversible l-bit ALUs using our proposed 3×3 and 4×4 reversible gates called MEB3 and MEB4 （Moallem Ehsanpour Bolhasani） gates, respectively. The first proposed reversible ALU consists of six logical operations. The second proposed ALU consists of eight operations, two arithmetic, and six logical operations. And finally, the third proposed ALU consists of sixteen operations, four arithmetic operations, and twelve logical operations. Our proposed ALUs can be used to construct efficient quantum computers in nanotechnology, because the proposed designs are better than the existing designs in terms of quantum cost, constant input, reversible gates used, hardware complexity, and functions generated.