Numerical Simulation of N+ Source Pocket PIN-GAA-Tunnel FET: Impact of Interface Trap Charges and Temperature

• Published in: IEEE transactions on electron devices Vol. 64; no. 4; pp. 1482 - 1488
• Main Authors: Madan, Jaya, Chaujar, Rishu
• Format: Journal Article
• Language: English
• Published: IEEE 01.04.2017
• Subjects: Data models; Electron traps; Interface trap charges (ITCs); Junctions; Logic gates; N⁺ source pocket; Reliability; temperature sensitivity; TFETs; tunnel FET (TFET); Tunneling

This paper investigates the reliability of PINgate-all-around (GAA)-tunnel field-effect transistor (TFET) with N± source pocket. The reliability of the PNIN-GAA-TFET is examined by analyzing: 1) the impact of interface trap charge (ITC) density and polarity and 2) the temperature affect ability on a...