Electrical Performance Depending on the Grain Boundary-location in the Multiple Nanosheet Tunneling Field-effect Transistor based on the Poly-Si

• Published in: Journal of semiconductor technology and science Vol. 23; no. 1; pp. 8 - 16
• Main Authors: Kang, Ga-Eon, Kang, In-Man, Lee, Sang-Ho, Park, Jin, Min, So-Ra, Kim, Geon-Uk, Heo, Jun-Hyeok, Jang, Jaewon, Bae, Jin-Hyuk, Lee, Sin-Hyung
• Format: Journal Article
• Language: English
• Published: 대한전자공학회 01.02.2023
• Subjects: 전기공학; polycrystalline silicon (Poly-Si); Multiple nanosheet tunneling field-effect transistor (MNSTFET); grain boundary (GB)
• DOI: 10.5573/JSTS.2023.23.1.8
• ISSN: 1598-1657

In this study, we present the electrical characteristics of the multiple nanosheet tunneling field-effect transistors (MNSTFETs) based on the polycrystalline silicon (poly-Si) depending on the grain boundary (GB)-locations. The effects of the GB are analyzed for 5 locations and they are compared with the device without the GB. When the GB was located in the tunneling region, the electrical performances were the most inferior compared with the device without the GB. In addition, it shows the electrical characteristics of 125 samples of the MNSTFETs compared with the multiple nanosheet metal-oxide-semiconductor field-effect transistors (MNSMOSFETs). The standard deviations (SDs) of the threshold voltage (VT) of MNSTFET and MNSMOSFET are 3.90 mV and 8.31 mV, respectively. If the GB is not located at 24 nm, the SDs of the average of subthreshold swing (SSave) are 1.50 mV/dec and 4.16 mV/dec, respectively. This simulation shows that the MNSTFET has smaller effect depending on the GB location than the MNSMOSFET. KCI Citation Count: 0