Empirical analysis of power side-channel leakage of high-level synthesis designed AES circuits

• Published in: International journal of reconfigurable and embedded systems Vol. 12; no. 3; p. 305
• Main Authors: Mizuno, Takumi, Nishikawa, Hiroki, Kong, Xiangbo, Tomiyama, Hiroyuki
• Format: Journal Article
• Language: English
• Published: Yogyakarta IAES Institute of Advanced Engineering and Science 01.11.2023
• Subjects: Circuit design; Circuits; Correlation coefficients; Countermeasures; Cybersecurity; Empirical analysis; High level synthesis; Integrated circuits; Internet of Things; Logic synthesis; Masking; Performance evaluation
• ISSN: 2089-4864; 2722-2608; 2089-4864
• DOI: 10.11591/ijres.v12.i3.pp305-319

Many internet of things (IoT) devices and integrated circuit (IC) cards have been compromised by side-channel attacks. Power-analysis attacks, which identify the secret key of a cryptographic circuit by analyzing the power traces, are among the most dangerous side-channel attacks. Gen-erally, there is a trade-off between execution time and circuit area. However, the correlation between security and performance has yet to be determined. In this study, we investigate the cor-relation between side-channel attack resistance and performance (execution time and circuit area) of advanced encryption standard (AES) circuits. Eleven AES circuits with different performances are designed by high-level synthesis and logic synthesis. Of the eleven AES circuits, six are circuits with no side-channel attack countermeasures and five are circuits with masking countermeasures. We employ four metrics based on a T-test to evaluate the side-channel attack resistance. The results based on the correlation coefficient show the correlation between side-channel attack resistance and performance. The correlation varies according to four metrics or masking countermeasure. We argue that designers should change their attitudes towards circuit design when considering security.