APA (7th ed.) Citation

Braga, G., Gonçalves, M. M., & Azambuja, J. R. (2023). Software-controlled pipeline parity in GPU architectures for error detection. Microelectronics and reliability, 148, 115155. https://doi.org/10.1016/j.microrel.2023.115155

Chicago Style (17th ed.) Citation

Braga, Giani, Marcio M. Gonçalves, and José Rodrigo Azambuja. "Software-controlled Pipeline Parity in GPU Architectures for Error Detection." Microelectronics and Reliability 148 (2023): 115155. https://doi.org/10.1016/j.microrel.2023.115155.

MLA (9th ed.) Citation

Braga, Giani, et al. "Software-controlled Pipeline Parity in GPU Architectures for Error Detection." Microelectronics and Reliability, vol. 148, 2023, p. 115155, https://doi.org/10.1016/j.microrel.2023.115155.