A novel design layout of three disjoint paths multistage interconnection network & its reliability analysis
PurposeThe purpose of this paper is to design a efficient layout of Multistage interconnection network which has cost effective solution with high reliability and fault-tolerence capability. For parallel computation, various multistage interconnection networks (MINs) have been discussed hitherto in...
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Published in | International journal of pervasive computing and communications Vol. 17; no. 4; pp. 390 - 403 |
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Main Authors | , , |
Format | Journal Article |
Language | English |
Published |
Bingley
Emerald Group Publishing Limited
21.09.2021
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Subjects | |
Online Access | Get full text |
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Abstract | PurposeThe purpose of this paper is to design a efficient layout of Multistage interconnection network which has cost effective solution with high reliability and fault-tolerence capability. For parallel computation, various multistage interconnection networks (MINs) have been discussed hitherto in the literature, however, these networks always required further improvement in reliability and fault-tolerance capability. The fault-tolerance capability of the network can be achieved by increasing the number of disjoint paths as a result the reliability of the interconnection networks is also improved.Design/methodology/approachThis proposed design is a modification of gamma interconnection network (GIN) and three disjoint path gamma interconnection network (3-DGIN). It has a total seven number of paths for all tag values which is uniform out of these seven paths, three paths are disjoint paths which increase the fault tolerance capability by two faults. Due to the presence of more paths than the GIN and 3-DGIN, this proposed design is more reliable.FindingsIn this study, a new design layout of a MIN has been proposed which provides three disjoint paths and uniformity in terms of an equal number of paths for all source-destination (S-D) pairs. The new layout contains fewer nodes as compared to GIN and 3-DGIN. This design provides a symmetrical structure, low cost, better terminal reliability and provides an equal number of paths for all tag values (|S-D|) when compared with existing MINs of this class.Originality/valueA new design layout of MINs has been purposed and its two terminal reliability is calculated with the help of the reliability block diagram technique. |
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AbstractList | PurposeThe purpose of this paper is to design a efficient layout of Multistage interconnection network which has cost effective solution with high reliability and fault-tolerence capability. For parallel computation, various multistage interconnection networks (MINs) have been discussed hitherto in the literature, however, these networks always required further improvement in reliability and fault-tolerance capability. The fault-tolerance capability of the network can be achieved by increasing the number of disjoint paths as a result the reliability of the interconnection networks is also improved.Design/methodology/approachThis proposed design is a modification of gamma interconnection network (GIN) and three disjoint path gamma interconnection network (3-DGIN). It has a total seven number of paths for all tag values which is uniform out of these seven paths, three paths are disjoint paths which increase the fault tolerance capability by two faults. Due to the presence of more paths than the GIN and 3-DGIN, this proposed design is more reliable.FindingsIn this study, a new design layout of a MIN has been proposed which provides three disjoint paths and uniformity in terms of an equal number of paths for all source-destination (S-D) pairs. The new layout contains fewer nodes as compared to GIN and 3-DGIN. This design provides a symmetrical structure, low cost, better terminal reliability and provides an equal number of paths for all tag values (|S-D|) when compared with existing MINs of this class.Originality/valueA new design layout of MINs has been purposed and its two terminal reliability is calculated with the help of the reliability block diagram technique. |
Author | Ansari, Abdul Q Sharma, Vipin Mishra, Rajesh |
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CitedBy_id | crossref_primary_10_1007_s11227_022_04735_6 crossref_primary_10_1149_2754_2726_acf328 crossref_primary_10_1149_2754_2734_acb786 |
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SubjectTerms | Block diagrams Communication Design modifications Fault tolerance Layouts Literature reviews Network reliability Parallel processing Reliability analysis |
Title | A novel design layout of three disjoint paths multistage interconnection network & its reliability analysis |
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