Coding for Improved Throughput Performance in Network Switches

• Published in: IEEE/ACM transactions on networking Vol. 25; no. 5; pp. 2802 - 2814
• Main Authors: Cohen, Rami, Cassuto, Yuval
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.10.2017; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithm design and analysis; Algorithms; coded network switches; combinatorial designs; Encoding; IEEE transactions; MDS codes; memory contention; Packet switching; Parallel processing; Placement; Random access memory; read throughput; router; Routers; Silicon; Switches; Throughput
• ISSN: 1063-6692; 1558-2566
• DOI: 10.1109/TNET.2017.2703118

Network switches and routers need to serve packet writes and reads at rates that challenge the most advanced memory technologies. As a result, scaling the switching rates is commonly done by parallelizing the packet I/Os using multiple memory units. For improved read rates, packets can be coded upon write, thus giving more flexibility at read time to achieve higher utilization of the memory units. This paper presents a detailed study of coded network switches, and in particular, how to design them to maximize the throughput advantages over standard uncoded switches. Toward that objective, the paper contributes a variety of algorithmic and analytical tools to improve and evaluate the throughput performance. The most interesting finding of this paper is that the placement of packets in the switch memory is the key to both high performance and algorithmic efficiency. One particular placement policy we call "design placement" is shown to enjoy the best combination of throughput performance and implementation feasibility.