Power-Line-Triggered ESD Protection SCR for 0-20 GHz Applications in CMOS Technology

• Published in: IEEE transactions on electron devices Vol. 70; no. 12; pp. 6103 - 6109
• Main Authors: Chang, Chun-Rong, Lin, Chun-Yu
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.12.2023; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Broadband; Circuit design; Circuit protection; Clamps; CMOS; CMOS process; Discharges (electric); electrostatic discharge (ESD); Electrostatic discharge protection; Electrostatic discharges; High speed; Inductors; Parasitic capacitance; Power lines; Robustness; Silicon controlled rectifiers; silicon-controlled rectifier (SCR)

The high-speed circuits fabricated in the CMOS process are sensitive to the electrostatic discharge (ESD), so the ESD protection circuits are required in the chips. The protection circuit should not seriously impact the performance of high-speed circuits and provide wider bandwidth. In this work, a...