Impact of CnRx Structure on Soft Error Rates of Flip-Flop Designs at 22-nm FD SOI Node

• Published in: IEEE transactions on nuclear science Vol. 70; no. 8; p. 1
• Main Authors: Elash, Christopher J., Li, Zongru, Jin, Chen, Chen, Li, Wen, Shi-Jie, Fung, Rita, Xing, Jiesi, Shi, Shuting, Yang, Zhi Wu, Bhuva, Bharat L.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.08.2023; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: CnRx; eSiGe; Flip-flop (FF); Flip-flops; fully depleted silicon on insulator (FDSOI); Germanium; Heavy ions; Hole mobility; Ion irradiation; Ions; Irradiation; Layout; Layouts; Logic gates; Radiation; radiation hardening by design; Silicon-on-insulator; single event upset; Soft errors; soft-error rate; SOI (semiconductors); Stacked Transistor; Strain; Transistors
• ISSN: 0018-9499; 1558-1578
• DOI: 10.1109/TNS.2023.3263770

Embedded Silicon Germanium (eSiGe) is used in the channel region of PFET devices at the 22-nm FD SOI node. The use of eSiGe results in channel regions becoming strained, which results in better hole mobility and increased performance. However, if the active diffusion regions are too short on each side of a PFET gate, then the effect of channel strain is reduced, and performance is reduced. The Continuous Active Diffusion (CnRx) layout construct suggested by the foundry is a way to help keep channel strain present within a single cell design. In this paper the CnRx construct is implemented in a 22-nm FD SOI test chip and soft error rates of stacked-transistor flip-flops are shown to increase with heavy ion irradiation. The effect of channel strain on PFETs results in higher collected charges from ion strikes, and charges are more easily passed between adjacent transistors through strained channels. However, with careful schematic and layout design, these effects can be mitigated to produce both high performance and radiation tolerant cells using the CnRx construct.