A 87.5-dB-SNDR Residue-integrated SAR ADC with a Digital-domain Capacitor Mismatch Calibration

• Published in: Journal of semiconductor technology and science Vol. 21; no. 2; pp. 143 - 151
• Main Authors: Ku, Hwan-Seok, Choi, Seungnam, Sim, Jae-Yoon
• Format: Journal Article
• Language: English
• Published: 대한전자공학회 01.04.2021
• Subjects: 전기공학; successive approximation register (SAR); high-resolution ADC; Analog-to-digital conversion (ADC); calibration
• ISSN: 1598-1657; 2233-4866
• DOI: 10.5573/JSTS.2021.21.2.143

This paper presents an asynchronous-clocking 16-bit successive approximation register (SAR) analog-to-digital converter (ADC) suitable for high-precision sensor applications. Comparator noise and nonlinearity from capacitor mismatch, as two major performance-limiting problems of SAR ADC, are resolved by noise averaging with a residue integration and a digital-domain capacitor error calibration, respectively. The proposed ADC is implemented using 180-nm CMOS technology in an area of 0.68mm2. The calibration improves SNDR by 5.9 dB and SFDR by 14.3 dB, achieving an SNDR of 87.5 dB and an SFDR of 106.85 dB, respectively. KCI Citation Count: 1