Diamond-Shaped e-SiGe Optimization by TCAD Simulation to Improve P-type MOSFET Performance for 28nm Logic Technology and Beyond

• Published in: ECS transactions Vol. 52; no. 1; pp. 61 - 66
• Main Authors: Wu, Hong, Pan, ZiCheng, Shi, XueJie, Lee, Byunghak, Ding, Yu, He, FengYing, Ye, Bin, Yu, TzuChiang, He, YongGen, Zhang, HaiYang, Yu, Shaofeng
• Format: Journal Article
• Language: English
• Published: 01.01.2013

The embedded-SiGe (e-SiGe) stressor has been an indispensable p-channel MOSFET (pFET) performance booster in the advanced logic technology nodes. In this work, we did extensive study by TCAD simulation on the optimization of the tip location, the Ge concentration profile, the in-situ doped B concent...