Multiple fault testing using minimal single fault test set for fanout-free circuits

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 12; no. 1; pp. 149 - 157
• Main Authors: Jone, W.-B., Madden, P.H.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.01.1993; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Computer science; Design. Technologies. Operation analysis. Testing; Electrical fault detection; Electronics; Exact sciences and technology; Fault detection; Integrated circuits; Laboratories; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Test pattern generators; Very large scale integration; Logic circuit; VLSI circuit; Integrated circuit; Test method; Failure detection; Algorithm; Time complexity
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/43.184851

The authors examine the properties of fanout-free circuits, and develop an algorithm to generate single stuck-at fault test experiments that also detect all multiple stuck-at faults. These experiments are shown to be minimal in size. Results demonstrate that elaborate selection of nonsensitizing test pattern guarantees the detection of all multiple stuck-at faults using single stuck-at test experiments. The algorithm is deterministic, and will produce test sets for tree circuits containing any mixture of AND, OR, NOT, NAND, and NOR gates. The results can be extensively applied to multiple stuck-at fault detection for pseudo tree circuits such as parity checkers. The time complexity of the algorithm is determined to the O(n/sup 2/), where n is the number of gates in the circuit.< >