Design of fault tolerant algorithm for network on chip router using field programmable gate array

• Published in: International journal of reconfigurable and embedded systems Vol. 13; no. 1; p. 1
• Main Authors: Shahane, Priti, Kurup, Rakhi
• Format: Journal Article
• Language: English
• Published: Yogyakarta IAES Institute of Advanced Engineering and Science 01.03.2024
• Subjects: Algorithms; Fault tolerance; Field programmable gate arrays; IP (Internet Protocol); Modules; Network latency; System on chip
• ISSN: 2089-4864; 2722-2608; 2089-4864
• DOI: 10.11591/ijres.v13.i1.pp1-8

Many internet protocol (IP) modules are present in contemporary system on chips (SoCs). This could provide an issue with interconnection among different IP modules, which would limit the system's ability to scale. Traditional bus-based SoC architectures have a connectivity bottleneck, and network on chip (NoC) has evolved as an embedded switching network to address this issue. The interconnections between various cores or IP modules on a chip have a significant impact on communication and chip performance in terms of power, area latency and throughput. Also, designing a reliable fault tolerant NoC became a significant concern. In fault tolerant NoC it becomes critical to identify faulty node and dynamically reroute the packets keeping minimum latency. This study provides an insight into a domain of NoC, with intention of understanding fault tolerant approach based on the XY routing algorithm for 4×4 mesh architecture. The fault tolerant NoC design is synthesized on Field programmable gate array (FPGA).