APA (7th ed.) Citation

Shahane, P., & Kurup, R. (2024). Design of fault tolerant algorithm for network on chip router using field programmable gate array. International journal of reconfigurable and embedded systems, 13(1), 1. https://doi.org/10.11591/ijres.v13.i1.pp1-8

Chicago Style (17th ed.) Citation

Shahane, Priti, and Rakhi Kurup. "Design of Fault Tolerant Algorithm for Network on Chip Router Using Field Programmable Gate Array." International Journal of Reconfigurable and Embedded Systems 13, no. 1 (2024): 1. https://doi.org/10.11591/ijres.v13.i1.pp1-8.

MLA (9th ed.) Citation

Shahane, Priti, and Rakhi Kurup. "Design of Fault Tolerant Algorithm for Network on Chip Router Using Field Programmable Gate Array." International Journal of Reconfigurable and Embedded Systems, vol. 13, no. 1, 2024, p. 1, https://doi.org/10.11591/ijres.v13.i1.pp1-8.