The Wave-Union Method on DSP Blocks: Improving FPGA-Based TDC Resolutions by 3x With a 1.5x Area Increase

• Published in: IEEE transactions on instrumentation and measurement Vol. 71; pp. 1 - 11
• Main Authors: Tancock, Scott, Rarity, John, Dahnoun, Naim
• Format: Journal Article
• Language: English
• Published: New York IEEE 2022; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Adders; Delay lines; Delays; Digital signal processing; Digital signal processing (DSP); Fabrics; Field programmable gate arrays; field-programmable gate array (FPGA); Multiplexing; Step response; Temperature gradients; Temperature measurement; time measurement; time-to-digital converter (TDC); wave union; Xilinx
• ISSN: 0018-9456; 1557-9662
• DOI: 10.1109/TIM.2022.3141753

Achieving high-resolution time-to-digital conversion is challenging at high count rates. In past work, the highest resolutions with low dead times (≤2 cycles) on field-programmable gate arrays (FPGAs) have been achieved using digital signal processing (DSP) blocks or using the wave-union method. In this article, we investigate the possibility of combining the wave-union method with DSP blocks. With the given configuration on a Xilinx Artix-7 200T FPGA, we achieve 13.60-ps single-shot precision (SSP) using only 3.78% of the FPGA fabric per channel (1.22% of the fabric in the finite step response (FSR) injector and 2.56% of the fabric in the delay line) for three edges, compared to 52.65 ps using 2.97% of the FPGA fabric per channel without the wave-union method. The scaling of edge numbers (for higher resolutions) is shown to be significantly better than the previously suggested parallel implementation, at just 0.407% of the FPGA fabric per edge compared to ~2.5% per edge in the parallel implementation. Temperature characterization showed an SSP penalty of just 4 ps over a 60 °C temperature difference.