Nested Miller compensation in low-power CMOS design
First, new stability conditions for low-power CMOS nested Miller compensated amplifiers are given in this brief. Then, an improved structure, which takes the advantages of a feedforward transconductance stage and a nulling resistor, is introduced. Experimental results prove that the proposed structu...
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| Published in | IEEE transactions on circuits and systems. 2, Analog and digital signal processing Vol. 48; no. 4; pp. 388 - 394 |
|---|---|
| Main Authors | , |
| Format | Journal Article |
| Language | English |
| Published |
New York
IEEE
01.04.2001
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subjects | |
| Online Access | Get full text |
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| Abstract | First, new stability conditions for low-power CMOS nested Miller compensated amplifiers are given in this brief. Then, an improved structure, which takes the advantages of a feedforward transconductance stage and a nulling resistor, is introduced. Experimental results prove that the proposed structure improves the frequency response, transient response, and power supply rejection ratio without increasing the power consumption and circuit complexity. |
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| AbstractList | First, new stability conditions for low-power CMOS nested Miller compensated amplifiers are given in this brief. Then, an improved structure, which takes the advantages of a feedforward transconductance stage and a nulling resistor, is introduced. Experimental results prove that the proposed structure improves the frequency response, transient response, and power supply rejection ratio without increasing the power consumption and circuit complexity. |
| Author | Mok, P.K.T. Ka Nang Leung |
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| SubjectTerms | Circuit testing Complexity theory Energy consumption Frequency response Parasitic capacitance Power supplies Resistors Stability Transconductance Transient response |
| Title | Nested Miller compensation in low-power CMOS design |
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