EF-CIM: An Endurance Friendly CIM Accelerator Using Embedded NVM With Bit-Aware Wear Leveling for Efficient Light-Weight On-Chip Training in Edge Devices - Guo, Zhiwang; Jiang, Jingwen; Chen, Deyang; Fang, Jinbei; Yang, Jianguo; Han, Jun; Xue, Xiaoyong; Zeng, Xiaoyang (IEEE transactions on circuits and systems. I, Regular papers, 2024)
Computing-in-memory (CIM) based on embedded nonvolatile memory (NVM) realizes energy-efficient acceleration of convolution neural network (CNN) with less data movement and high computing parallelism. Because the deployment environments for edge devices are usually subject to changes, it is necessary for the CIM accelerators to support light-weight on-chip training with efficient implementation for environmental adaptation. However, previous CIM accelerators for edge devices mainly realize the inference while the training is performed on cloud. The limited endurance of NVMs hinders the CIM accelerators from supporting on-chip training that involves a large number of weight updates. In this paper, an endurance friendly CIM accelerator based on NVM, EF-CIM, is presented with bit-aware wear-leveling for efficient on-chip training in edge devices. Firstly, the bit split weight mapping (BSWM) splits the multi-bit weights into individual bits and stores them in the array alternately. Then, the bit-aware wear-leveling (BAWL) reduces the NVM updates by using verify write and block switch methods. An EF-CIM accelerator with BSWM and BAWL that is evaluated for 8-bit inputs and weights in the 28nm process achieves \sim 3.58/3.26 TOPS/W energy efficiency for feed-forward/ back-propagation, 5X lower computing latency. The BAWL also alleviates the wear of NVMs by 40X, achieving high NVM training reliability.