RESEARCH ON THE PACKING ALGORITHM FOR ANTI-SEU OF FPGA BASED ON TRIPLE MODULAR REDUNDANCY AND THE NUMBERS OF FAN-OUTS OF THE NET

• Published in: Journal of electronics (China) Vol. 31; no. 4; pp. 284 - 289
• Main Authors: Cui, Xiuhai, Yang, Haigang, Peng, Yu, Peng, Xiyuan
• Format: Journal Article
• Language: English
• Published: Heidelberg Science Press 01.08.2014; Automatic Test and Control Institute, Harbin Institute of Technology, Harbin 150001, China; Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China%Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China%Automatic Test and Control Institute, Harbin Institute of Technology, Harbin 150001, China
• Subjects: Electrical Engineering; Engineering; Field Programmable Gate Array (FPGA); Fan-outs of the net; Packing algorithm; TN473; Triple Modular Redundancy (TMR); Critical path delay
• ISSN: 0217-9822; 1993-0615
• DOI: 10.1007/s11767-014-4051-4

Static Random Access Memory （SRAM） based Field Programmable Gate Array （FPGA） is widely applied in the field of aerospace,whose anti-SEU （Single Event Upset） capability becomes more and more important.To improve anti-FPGA SEU capability,the registers of the circuit netlist are tripled and divided into three categories in this study.By the packing algorithm,the registers of triple modular redundancy are loaded into different configurable logic block.At the same time,the packing algorithm considers the effect of large fan-out nets.The experimental results show that the algorithm successfully realize the packing of the register of Triple Modular Redundancy （TMR）.Comparing with Timing Versatile PACKing （TVPACK）,the algorithm in this study is able to obtain a 11％ reduction of the number of the nets in critical path,and a 12％ reduction of the time delay in critical path on average when TMR is not considered.Especially,some critical path delay of circuit can be improved about 33％.