TIMING SLACK OPTIMIZATION APPROACH USING FPGA HYBRID ROUTING STRATEGY OF RIP-UP-RETRY AND PATHFINDER

• Published in: Journal of electronics (China) Vol. 31; no. 3; pp. 246 - 255
• Main Authors: Yu, Wei, Yang, Haigang, Liu, Yang, Huang, Juan
• Format: Journal Article
• Language: English
• Published: Heidelberg Science Press 2014; University of Chinese Academy of Sciences, Beijing 100049, China%Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China
• Subjects: Electrical Engineering; Engineering; Field Programmable Gate Array (FPGA); Routing; Slack; TN702; Timing analysis
• ISSN: 0217-9822; 1993-0615
• DOI: 10.1007/s11767-014-4013-x

To improve the path slack of Field Programmable Gate Array （FPGA）, this paper proposes a timing slack optimization approach which utilizes the hybrid routing strategy of rip-up-retry and pathfinder. Firstly, effect of process variations on path slack is analyzed, and by constructing a col- location table of delay model that takes into account the multi-corner process, the complex statistical static timing analysis is successfully translated into a simple classical static timing analysis. Then, based on the hybrid routing strategy of rip-up-retry and pathfinder, by adjusting the critical path which detours a long distance, the critical path delay is reduced and the path slack is optimized. Experimental results show that, using the hybrid routing strategy, the number of paths with negative slack can be optimized （reduced） by 85.8% on average compared with the Versatile Place and Route （VPR） tim- ing-driven routing algorithm, while the run-time is only increased by 15.02% on average.