Quick-low-density parity check and dynamic threshold voltage optimization in 1X nm triple-level cell NAND flash memory with comprehensive analysis of endurance, retention-time, and temperature variation

• Published in: Japanese Journal of Applied Physics Vol. 55; no. 8; pp. 84201 - 84210
• Main Authors: Doi, Masafumi, Tokutomi, Tsukasa, Hachiya, Shogo, Kobayashi, Atsuro, Tanakamaru, Shuhei, Ning, Sheyang, Iwasaki, Tomoko Ogura, Takeuchi, Ken
• Format: Journal Article
• Language: English
• Published: The Japan Society of Applied Physics 01.08.2016

NAND flash memory s reliability degrades with increasing endurance, retention-time and/or temperature. After a comprehensive evaluation of 1X nm triple-level cell (TLC) NAND flash, two highly reliable techniques are proposed. The first proposal, quick low-density parity check (Quick-LDPC), requires...