High Level Synchronization and Computations of Feed Forward Cut-Set based Multiply Accumulate Unit

• Published in: Journal of physics. Conference series Vol. 1804; no. 1; p. 12201
• Main Authors: Srikanth, I, Aunmetha, S
• Format: Journal Article
• Language: English
• Published: Bristol IOP Publishing 01.02.2021
• Subjects: Computer architecture; Critical path; Delay; Digital signal processing; Logic circuits; Performance enhancement; Physics; Power consumption; Synchronism
• ISSN: 1742-6588; 1742-6596
• DOI: 10.1088/1742-6596/1804/1/012201

Abstract In a modern technology-based application, digital signal processing (DSP) is a major priority one, in this gadgets application, the Multiply Accumulate Unit (MAC) will occupy more memory usages, power consumptions and critical path delay. Due to the number of arithmetic operations, this MAC unit will play’s a major role in this application product. Thus, the pipelined based architecture will be used to reduce the number of critical paths delay and to improve the performance of MAC architecture. However, the number of flip flops will be increased in the MAC unit, due to number of pipelined architectures. Consequently, it will increase the area and the power consumption. Thus, proposed work of this paper will get a novelty process of feed forward cut-set based MAC architecture with high level synchronization of XOR-MUX full adder with compressor technique. It will reduce the number of logic gates in MAC architecture and hence prove the performance in FPGA Implementation of LUT based area, critical path delay and average power consumption.