An 80 dB Second-order Noise Shaping SAR ADC using Differential Integral Capacitors and Comparator with Voltage Gain Calibration

• Published in: Journal of semiconductor technology and science Vol. 22; no. 4; pp. 205 - 215
• Main Authors: Jung, Hoyong, Jeon, Neungin, Cheon, Jimin, Jang, Young-Chan
• Format: Journal Article
• Language: English
• Published: 대한전자공학회 01.08.2022
• Subjects: 전기공학; Successive approximation register; analog-to-digital converter; voltage gain calibration; noise shaping; differential capacitor
• ISSN: 1598-1657; 2233-4866
• DOI: 10.5573/JSTS.2022.22.4.205

A second-order noise shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) is proposed for sensor interface applications. It consists of a capacitor-resistor hybrid digital-to-analog-converter (C-R DAC) with 10-bit resolution, a comparator with three inputs, a SAR logic, and a second passive integrator using two differential capacitors. The use of a C-R DAC and two differential capacitors reduces the capacitor area of the conventional NS SAR ADC by 86.25%. Voltage gain calibration for the three-input comparator is proposed to maximize the performance of the NS SAR ADC. The proposed second-order NS ADC is designed using a 180-nm CMOS process with a supply of 1.8 V. The proposed second-order NS SAR ADC with an over sampling ratio of 8 has a SNDR of 80.18 dB and an ENOB of 13.03 bits. Its area and power consumption are 0.165 mm2 and 248 μW, respectively. KCI Citation Count: 0