APA (7th ed.) Citation

Min, K., Lee, S., & Oh, T. (2021). High-speed Clock and Data Recovery System with Segmented Slew-rate Control Circuit for High-linearity in 65 nm CMOS Process. Journal of semiconductor technology and science, 21(3), 199-205. https://doi.org/10.5573/JSTS.2021.21.3.199

Chicago Style (17th ed.) Citation

Min, Kyunghwan, Sanggeun Lee, and Taehyoun Oh. "High-speed Clock and Data Recovery System with Segmented Slew-rate Control Circuit for High-linearity in 65 Nm CMOS Process." Journal of Semiconductor Technology and Science 21, no. 3 (2021): 199-205. https://doi.org/10.5573/JSTS.2021.21.3.199.

MLA (9th ed.) Citation

Min, Kyunghwan, et al. "High-speed Clock and Data Recovery System with Segmented Slew-rate Control Circuit for High-linearity in 65 Nm CMOS Process." Journal of Semiconductor Technology and Science, vol. 21, no. 3, 2021, pp. 199-205, https://doi.org/10.5573/JSTS.2021.21.3.199.