Extension of DRAM Retention Time at 77 Kelvin by Replacing Weak Rows with Large GIDL Current

• Published in: Journal of semiconductor technology and science Vol. 22; no. 3; pp. 133 - 138
• Main Authors: Kim, Ho-Jun, Lee, Won-Cheol, Park, Hong-June
• Format: Journal Article
• Language: English
• Published: 대한전자공학회 01.06.2022
• Subjects: 전기공학; DRAM controller; cryogenic memory; DRAM refresh; retention time; cryogenic temperature

At 77 Kelvin, it was found that the weak cells with large gate-induced drain leakage current are quite localized in six weak rows out of the entire 524,288 rows of a 8 Gb DRAM chip. By replacing the six weak rows, the DRAM retention time was increased from 8 to 4096 seconds at 77 Kelvin. Because thi...