Extension of DRAM Retention Time at 77 Kelvin by Replacing Weak Rows with Large GIDL Current

• Published in: Journal of semiconductor technology and science Vol. 22; no. 3; pp. 133 - 138
• Main Authors: Kim, Ho-Jun, Lee, Won-Cheol, Park, Hong-June
• Format: Journal Article
• Language: English
• Published: 대한전자공학회 01.06.2022
• Subjects: 전기공학; DRAM controller; cryogenic memory; DRAM refresh; retention time; cryogenic temperature
• ISSN: 1598-1657; 2233-4866
• DOI: 10.5573/JSTS.2022.22.3.133

At 77 Kelvin, it was found that the weak cells with large gate-induced drain leakage current are quite localized in six weak rows out of the entire 524,288 rows of a 8 Gb DRAM chip. By replacing the six weak rows, the DRAM retention time was increased from 8 to 4096 seconds at 77 Kelvin. Because this retention time is over 64,000 times longer than the JEDEC retention-time specification of 0.064 seconds, the DRAM refresh power can be reduced to a negligible level at the data center. To achieve this, the DRAM controller was modified to find weak rows by using three different data patterns at power-on reset and a reserved row of DRAM is used when access to a weak row address occurs during the normal operation. KCI Citation Count: 0