2 Lanes × 2.65-6.4 Gb/s Scalable IO Transceiver with Delay Compensation Technique in 65 nm CMOS Process - Chung, Goohyung; Cho, Kyoungub; Oh, Taehyoun (Journal of semiconductor technology and science, 2024)
A Delay compensation technique for implementing scalable high-speed logics has been proposed and its theoretical background has been analyzed fundamentally. Based on the scalable design methodology, the whole logics of proposed 2-channel transceiver operate successfully over the range of 2.65-6.4 Gb/s. The prototype chip has been fabricated in 65 nm CMOS process and occupies 1.02 mm2 die area. The transceiver consumes 72 mW/lane from 1.2 V supply. The measured eye-openings show 28.7% improvement vertically in Tx output by pre-emphasis at 6.4 Gb/s. The built-in Rx BER counter shows 0.25 unit interval (UI) horizontal eye-opening improvement at 10-9 BER in this speed. KCI Citation Count: 0