10T SRAM Using Half- V} Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 25; no. 4; pp. 1193 - 1203
• Main Authors: Maroof, Naeem, Bai-Sun Kong
• Format: Journal Article
• Language: English; Japanese
• Published: IEEE 01.04.2017
• Subjects: 10T; charge recycling; Leakage currents; leakage reduction; low power; Power dissipation; precharging; Rails; Sensors; single ended (SE) read bitline (RBL); SRAM cells; static random access memory (SRAM); Transistors; virtual rails

We present, in this paper, a new 10T static random access memory cell having single ended decoupled read-bitline (RBL) with a 4T read port for low power operation and leakage reduction. The RBL is precharged at half the cell's supply voltage, and is allowed to charge and discharge according to...