ALT-Lock: Logic and Timing Ambiguity-Based IP Obfuscation Against Reverse Engineering

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 32; no. 8; pp. 1535 - 1548
• Main Authors: Talukdar, Jonti, Paik, Woo-Hyun, Ortega, Eduardo, Chakrabarty, Krishnendu
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.08.2024; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Ambiguity; Gates; Hardware security; intellectual property (IP) security; Locking; Logic; Logic circuits; Logic gates; Reverse engineering; Security; standard cells; supply chain security; Supply chains; Threat modeling; Timing; timing obfuscation; Very large scale integration
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2024.3411033

We present a logic ambiguity-based intellectual property (IP) obfuscation method that replaces traditional key gates with key-controlled functionally ambiguous logic gates, called LGA gates. We also protect timing paths by developing timing-ambiguous sequential cells called TA cells. We call this locking scheme ambiguous logic and timing logic locking (referred to as ALT-Lock). ALT-Lock ensures a two-pronged system-level security scheme where the attacker is forced to unlock not only combinational logic obfuscation but also timing obfuscation. We show that a combination of logic and timing ambiguity (TA) provides security against oracle-guided attacks. This method is superior to other traditional IP protection schemes such as combinational or sequential locking as it guarantees security against both oracle-guided and oracle-free attacks, while ensuring low power, performance, and area (PPA) overhead.