Redesigning CMOS VLSI using Yosys synthesis tool

• Published in: Informatika (Minsk, Belarus) Vol. 22; no. 1; pp. 27 - 39
• Main Authors: Cheremisinov, D. I., Cheremisinova, L. D.
• Format: Journal Article
• Language: English; Russian
• Published: National Academy of Sciences of Belarus, the United Institute of Informatics Problems 31.03.2025
• Subjects: reverse engineering, decompilation of transistor circuits, cmos circuits, spice format, language verilog, package yosys
• ISSN: 1816-0301; 2617-6963
• DOI: 10.37661/1816-0301-2025-22-1-27-39

Objectives . The problem of reverse engineering of a transistor level circuit specified in the SPICE format in a different technological basis is considered. The goal of the work is to develop an approach to redesigning circuits using open source design automation software packages. Methods. A method is proposed based on extracting the structure at the level of logical elements from a flat SPICE description of a transistor circuit and exporting the resulting hierarchical SPICE description to the software environment of the open synthesis package Yosys. The purpose of the export is to transform the description of the logical network in the SPICE format into descriptions in the input languages of design automation systems, as well as to perform optimization and synthesis operations in the Yosys environment. Results. To export a logical network specified in the SPICE format to the core of the Yosys package, a program in C++ was developed using the classes of the Yosys package. The program accepts and processes the hierarchical SPICE description of the logical network, translating it into a representation in the internal format of the Yosys tool. Conclusion . The developed program is designed as a Yosys program module and integrated into its environment as one of its commands. All the transformations available in Yosys can be performed on the logical network structure obtained by the module.