Fast time-to-market with via-configurable transistor array regular fabric: A delay-locked loop design case study

• Published in: 2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) pp. 1 - 6
• Main Authors: Pons, M., Barajas, E., Mateo, D., Gonzalez, J. L., Moll, F., Rubio, A., Abella, J., Vera, X., Gonzalez, A.
• Format: Conference Proceeding Publication
• Language: English
• Published: IEEE 01.04.2011; IEEE Computer Society Publications
• Subjects: Arquitectura de computadors; Circuit Analysis; Computer architecture; Delay; Delay Lock Loops; Design Methodology; Informàtica; Integrated circuit layout; Jitter; Layout; Manufacturing; Metals; Microprocessadors; Microprocessors; Transistors; Àrees temàtiques de la UPC

Time-to-market is a critical issue for nowadays integrated circuits manufacturers. In this paper the Via-Configurable Transistor Array regular layout fabric (VCTA), which aims to minimize the time-to-market and its associated costs, is studied for a Delay-Locked Loop design (DLL). The comparison wit...