Fast time-to-market with via-configurable transistor array regular fabric: A delay-locked loop design case study

Time-to-market is a critical issue for nowadays integrated circuits manufacturers. In this paper the Via-Configurable Transistor Array regular layout fabric (VCTA), which aims to minimize the time-to-market and its associated costs, is studied for a Delay-Locked Loop design (DLL). The comparison wit...

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Published in2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) pp. 1 - 6
Main Authors Pons, M., Barajas, E., Mateo, D., Gonzalez, J. L., Moll, F., Rubio, A., Abella, J., Vera, X., Gonzalez, A.
Format Conference Proceeding Publication
LanguageEnglish
Published IEEE 01.04.2011
IEEE Computer Society Publications
Subjects
Arquitectura de computadors
Circuit Analysis
Computer architecture
Delay
Delay Lock Loops
Design Methodology
Informàtica
Integrated circuit layout
Jitter
Layout
Manufacturing
Metals
Microprocessadors
Microprocessors
Transistors
Àrees temàtiques de la UPC
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Summary:Time-to-market is a critical issue for nowadays integrated circuits manufacturers. In this paper the Via-Configurable Transistor Array regular layout fabric (VCTA), which aims to minimize the time-to-market and its associated costs, is studied for a Delay-Locked Loop design (DLL). The comparison with a full custom design demonstrates that VCTA can be used without loss of functionality while accelerating the design time. Layout implementations, in 90 nm CMOS process, as well as the delay, energy and jitter electrical simulations are provided.
ISBN:9781612848990
1612848990
DOI:10.1109/DTIS.2011.5941428