Dynamic-vector execution on a general purpose EDGE chip multiprocessor

• Published in: 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV) pp. 18 - 25
• Main Authors: Duric, Milovan, Palomar, Oscar, Smith, Aaron, Stanic, Milan, Unsal, Osman, Cristal, Adrian, Valero, Mateo, Burger, Doug, Veidenbaum, Alex
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.07.2014
• Subjects: Computational modeling; Computer architecture; Hardware; Instruction sets; Message systems; Registers; Vectors

This paper proposes a cost-effective technique that morphs the available cores of a low power chip multiprocessor (CMP) into an accelerator for data parallel (DLP) workloads. Instead of adding a special-purpose vector architecture as an accelerator, our technique leverages the resources of each CMP...