A 7-nm 4-GHz Arm¹-Core-Based CoWoS¹ Chiplet Design for High-Performance Computing
We present a dual-chiplet interposer-based system-in-package (SiP) octo-core processor using Chip-on-Wafer-on-Substrate (CoWoS) technology. Each of the two identical chiplets is implemented in 7-nm CMOS with 15 metal layers and has four Arm Cortex-A72 processor cores operating at 4.0 GHz. A bidirect...
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Published in | IEEE journal of solid-state circuits Vol. 55; no. 4; pp. 956 - 966 |
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Main Authors | , , , , , , , , , , , , , , , , |
Format | Journal Article |
Language | English |
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New York
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
01.04.2020
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Abstract | We present a dual-chiplet interposer-based system-in-package (SiP) octo-core processor using Chip-on-Wafer-on-Substrate (CoWoS) technology. Each of the two identical chiplets is implemented in 7-nm CMOS with 15 metal layers and has four Arm Cortex-A72 processor cores operating at 4.0 GHz. A bidirectional mesh bus with 2-mm flop-to-flop distance is distributed throughout the chiplet for high-speed on-die data transport above 4.0 GHz. The chiplets communicate with each other through ultrashort reach (0.5 mm long) interposer channels using a Low-voltage-In-Package-INterCONnect (LIPINCON) clock-forwarded parallel interface. The scalable link module offers 320 GB/s of aggregate bandwidth, operating at 8.0 Gb/s/pin and 0.3-V transmitter swing without receiver termination to achieve 0.56-pJ/bit energy efficiency and 1.6-Tb/s/mm2 bandwidth density. Measurements of the fabricated SiP validate the functionality and performance of the cores, on-die data bus, and inter-chiplet link. The built-in LIPINCON eye-scan feature validates inter-chiplet connectivity at 8.0 Gb/s with an eye opening of 244 mV and 0.69 UI. |
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AbstractList | We present a dual-chiplet interposer-based system-in-package (SiP) octo-core processor using Chip-on-Wafer-on-Substrate (CoWoS) technology. Each of the two identical chiplets is implemented in 7-nm CMOS with 15 metal layers and has four Arm Cortex-A72 processor cores operating at 4.0 GHz. A bidirectional mesh bus with 2-mm flop-to-flop distance is distributed throughout the chiplet for high-speed on-die data transport above 4.0 GHz. The chiplets communicate with each other through ultrashort reach (0.5 mm long) interposer channels using a Low-voltage-In-Package-INterCONnect (LIPINCON) clock-forwarded parallel interface. The scalable link module offers 320 GB/s of aggregate bandwidth, operating at 8.0 Gb/s/pin and 0.3-V transmitter swing without receiver termination to achieve 0.56-pJ/bit energy efficiency and 1.6-Tb/s/mm2 bandwidth density. Measurements of the fabricated SiP validate the functionality and performance of the cores, on-die data bus, and inter-chiplet link. The built-in LIPINCON eye-scan feature validates inter-chiplet connectivity at 8.0 Gb/s with an eye opening of 244 mV and 0.69 UI. |
Author | Tsai, Chien-Chun Yang, Sheng-Yao Rusu, Stefan Hsieh, Kenny Cheng-Hsiang Lin, Mu-Shan Chen, Ching-Fang Yang, Shu-Chun Hu, Chi-Wei Fu, Chin-Ming Lee, Frank Tam, King-Ho Li, Chao-Chieh Huang, Wen-Hung Wong, Mei Chen, Yu-Chi Huang, Tze-Chiang Goel, Sandeep Kumar |
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Cites_doi | 10.1109/IEDM.2016.7838333 10.1109/ISSCC.2018.8310173 10.23919/VLSIT.2017.7998198 10.23919/VLSIC.2019.8778161 |
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Title | A 7-nm 4-GHz Arm¹-Core-Based CoWoS¹ Chiplet Design for High-Performance Computing |
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