ReDeSIGN: Re use of De bug S tructures for I mprovement in Performance G ain of N oC Based MPSoCs

• Published in: IEEE transactions on emerging topics in computing Vol. 11; no. 2; pp. 432 - 447
• Main Authors: Rout, Sidhartha Sankar, M, Badri, Sinha, Mitali, Deb, Sujay
• Format: Journal Article
• Language: English
• Published: New York The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 01.04.2023
• Subjects: Hardware; Mass production; Modules; Multiprocessing; Network latency; Performance enhancement; Redesign; System on chip
• ISSN: 2168-6750; 2168-6750
• DOI: 10.1109/TETC.2022.3203611

Network-on-Chip (NoC) is considered as a scalable interconnect medium for Multiprocessor System-on-Chip (MPSoC) due to its ability to provide high bandwidth and low latency communication. With the increasing intricacy of the modern-day systems, the state-of-the-art NoCs are becoming extremely complex. Design-for-Debug (DFD) structures are integrated to the system for the validation of such complex modules during post-silicon debug. However, after the system validation and mass production, the DFD hardware remains vestigial on the design. In this context, we propose ReDeSIGN, a framework to reuse the DFD infrastructure during the in-field operation for performance enhancement of the NoC-based MPSoCs. Major contributions of our work include reuse of (i) trace buffer as extended Virtual Channel (VC) for network throughput improvement, (ii) trace prioritization hardware for critical data prioritization, and (iii) packet monitor module for packet starvation control. Experimental evaluations with real benchmarks show an average of 11.46% increase in network throughput, 34.93% decrease in critical data latency, and 19.17% decrease in packet starvation for an 8x8 homogeneous system.