A Priority-Aware Multiqueue NIC Design

• Published in: arXiv.org
• Main Authors: Behnke, Ilja, Wiesner, Philipp, Danicki, Robert, Thamsen, Lauritz
• Format: Paper Journal Article
• Language: English
• Published: Ithaca Cornell University Library, arXiv.org 03.01.2022
• Subjects: Computer Science - Distributed, Parallel, and Cluster Computing; Computer Science - Hardware Architecture; Computer Science - Networking and Internet Architecture; Computer Science - Operating Systems; Embedded systems; Flow mapping; Industrial applications; Internet of Things; Interrupts; IP (Internet Protocol); Queues; Real time
• ISSN: 2331-8422
• DOI: 10.48550/arxiv.2201.00594

Low-level embedded systems are used to control cyber-phyiscal systems in industrial and autonomous applications. They need to meet hard real-time requirements as unanticipated controller delays on moving machines can have devastating effects. Modern developments such as the industrial Internet of Things and autonomous machines require these devices to connect to large IP networks. Since Network Interface Controllers (NICs) trigger interrupts for incoming packets, real-time embedded systems are subject to unpredictable preemptions when connected to such networks. In this work, we propose a priority-aware NIC design to moderate network-generated interrupts by mapping IP flows to processes and based on that, consolidates their packets into different queues. These queues apply priority-dependent interrupt moderation. First experimental evaluations show that 93% of interrupts can be saved leading to an 80% decrease of processing delay of critical tasks in the configurations investigated.