A methodology to improve timing yield in the presence of process variations

• Published in: 2004 41st Conference Design Automation pp. 448 - 453
• Main Authors: Raj, Sreeja, Vrudhula, Sarma B. K., Wang, Janet
• Format: Conference Proceeding
• Language: English
• Published: New York, NY, USA ACM 01.01.2004; IEEE; Association for Computing Machinery
• Series: ACM Conferences
• Subjects: Applied sciences; Circuits; Delay; Design methodology; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Fabrication; Hardware > Hardware validation; Integrated circuits; Low power electronics; Microelectronic fabrication (materials and surfaces technology); Random variables; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Size control; Timing; Uncertainty; Yield estimation; timing yield; gate sizing; timing analysis; Performance evaluation; Monte Carlo method; Circuit design; Integrated circuit design; Algorithm; Optimization; Dimensioning; Statistical method; Microelectronic fabrication; Manufacturing process; Critical path; Numerical simulation; Delay time; CMOS integrated circuits; Deterministic approach; Random variable; Computer aided design
• ISBN: 1581138288; 9781581138283; 1511838288
• ISSN: 0738-100X
• DOI: 10.1145/996566.996694

The ability to control the variations in IC fabrication process is rapidly diminishing as feature sizes continue towards the sub-100 nm regime. As a result, there is an increasing uncertainty in the performance of CMOS circuits. Accounting for the worst case values of all parameters will result in an unacceptably low timing yield. Design for Variability, which involves designing to achieve a given level of confidence in the performance of ICs, is fast becoming an indispensable part of IC design methodology. This paper describes a method to identify certain paths in the circuit that are responsible for the spread of timing performance. The method is based on defining a disutility function of the gate and path delays, which includes both the means and variances of the delay random variables. Based on the moments of this disutility function, an algorithm is presented which selects a subset of paths (called undominated paths) as being most responsible for the variation in timing performance. Next, a statistical gate sizing algorithm is presented, which is aimed at minimizing the delay variability of the nodes in the selected paths subject to constraints on the critical path delay and the area penalty. Monte-Carlo simulations with ISCAS '85 benchmark circuits show that our statistical optimization approach results in significant improvements in timing yield over traditional deterministic sizing methods.