Bouquet of Instruction Pointers: Instruction Pointer Classifier-based Spatial Hardware Prefetching

• Published in: 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA) pp. 118 - 131
• Main Authors: Pakalapati, Samuel, Panda, Biswabandan
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.05.2020
• Subjects: Benchmark testing; Caching; Computer architecture; Hardware; Hardware Prefetching; Microarchitecture; Multicore processing; Prefetching; Proposals; Random access memory; Spatial databases
• DOI: 10.1109/ISCA45697.2020.00021

Hardware prefetching is one of the common off-chip DRAM latency hiding techniques. Though hardware prefetchers are ubiquitous in the commercial machines and prefetching techniques are well studied in the computer architecture community, the "memory wall" problem still exists after decades...