Applied Reconfigurable Computing 11th International Symposium, ARC 2015, Bochum, Germany, April 13-17, 2015, Proceedings

This book constitutes the refereed proceedings of the 11th International Symposium on Applied Reconfigurable Computing, ARC 2015, held in Bochum, Germany, in April 2015. The 23 full papers and 20 short papers presented in this volume were carefully reviewed and selected from 85 submissions. They are...

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Bibliographic Details
Main Authors Sano, Kentaro, Soudris, Dimitrios, Hübner, Michael, Diniz, Pedro C
Format eBook Book Conference Proceeding
LanguageEnglish
Published Cham Springer Nature 2015
Springer
Springer International Publishing AG
Springer International Publishing
Edition1
SeriesLecture Notes in Computer Science
Subjects
Adaptive computing systems
Adaptive computing systems-Congresses
Algorithm Analysis and Problem Complexity
ARC
Artificial Intelligence
Computer Hardware
Computer programming, programs, data
Computer Science
Computer Systems Organization and Communication Networks
Field programmable gate arrays
Hardware Architecture
Information Systems Applications (incl. Internet)
Online AccessGet full text
ISBN3319162144
9783319162140
3319162136
9783319162133
ISSN0302-9743
1611-3349
DOI10.1007/978-3-319-16214-0

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Table of Contents:
  • Intro -- Preface -- Organization -- Contents -- Architecture and Modeling -- Reducing Storage Costs of Reconfiguration Contexts by Sharing Instruction Memory Cache Blocks -- 1 Introduction -- 2 Related Work -- 3 Demand-Based Cache Memory Block Manager (DCMBM) -- 3.1 The Structure of the Cache Memory -- 3.2 Block Allocation Hardware -- 3.3 Replacement Algorithm -- 4 Case Study -- 4.1 DIM Architecture -- 4.2 Employment of DCMBM in the DIM Architecture -- 5 Experimental Results -- 5.1 Same Storage Capacity -- 5.2 Halve the Storage Capacity -- 6 Conclusions -- References -- A Vector Caching Scheme for Streaming FPGA SpMV Accelerators -- 1 Introduction -- 2 Background and Related Work -- 2.1 The SpMV Kernel and Sparse Matrix Storage -- 2.2 FPGA SpMV Accelerators and Result Vector Access -- 2.3 Sparse Matrix Preprocessing -- 3 Vector Caching Scheme -- 3.1 Row Lifetime Analysis -- 3.2 Avoiding Vector Cache Misses -- 3.3 Preprocessing -- 3.4 Vector Cache Design -- 4 Experimental Evaluation -- 4.1 OCM Savings Analysis -- 4.2 Vector Cache Evaluation -- 5 Conclusion and Future Work -- References -- Hierarchical Dynamic Power-Gating in FPGAs -- 1 Introduction -- 2 Context -- 2.1 Dynamic Power-Gated Architecture -- 2.2 LegUp High-Level Synthesis Framework -- 3 Hierarchical Power-Gating -- 3.1 Identifying Accelerator Hierarchy -- 3.2 Idle Period Detection -- 3.3 Pruning Idle Periods -- 3.4 Power-gating Schedule Generation -- 4 Experimental Results -- 4.1 Experimental Setup -- 4.2 Hierarchical Power-Gating Evaluation -- 4.3 Impact of Power-Gating on Execution Run-time -- 5 Impact of Input Patterns on Static Power-Gating Decisions -- 6 Conclusion and Future Work -- References -- Tools and Compilers I -- Hardware Synthesis from Functional Embedded Domain-Specific Languages: A Case Study in Regular Expression Compilation -- 1 Introduction
  • 4.4 Data Processing by Microblazes
  • 4 Activity Recording -- Stream Sources -- 4.1 Explicit Writing to a Timed Stream -- 4.2 Block-Based Annotations -- 5 Run-Time Extra-Functional Property Monitoring -- Stream Processing -- 5.1 Time Normalisation of Streams -- 5.2 Offline Analysis -- Stream Backends -- 6 Conclusion -- References -- Run-Time Partial Reconfiguration Simulation Framework Based on Dynamically Loadable Components -- 1 Introduction -- 1.1 Dynamic Reconfiguration in SystemC -- 2 Related Works -- 3 Simulation Framework -- 3.1 Heterogeneous Component Integration -- 3.2 Communication Adapter Architecture -- 3.3 Partial Dynamic Run-Time Reconfiguration -- 3.4 Reconfigurable Unit Architecture -- 3.5 Reconfiguration Controller -- 3.6 Location Service -- 4 Experimental Results -- 5 Conclusions -- References -- Network-on-a-Chip -- Architecture Virtualization for Run-Time Hardware Multithreading on Field Programmable Gate Arrays -- 1 Introduction -- 2 Motivation Example -- 3 Related Work -- 4 The Novel Architecture -- 4.1 General Device Organization -- 4.2 Processing Elements -- 4.3 Router Architecture -- 4.4 Quattuor-PE Direct Interconnect -- 5 Evaluation -- 6 Conclusion and Future Work -- References -- Centralized and Software-Based Run-Time Traffic Management Inside Configurable Regions of Interest in Mesh-Based Networks-on-Chip -- 1 Introduction -- 2 Related work -- 3 Quadran T-Based Mesh Topology -- 4 Regional Traffic Monitoring -- 5 Software-Based Run-Time Adaption of Routing Paths -- 6 Experimental Results -- 6.1 Reliability Analysis -- 6.2 Traffic Analysis -- 7 Conclusion -- References -- Survey on Real-Time Network-on-Chip Architectures -- 1 Introduction -- 2 Real-Time Challenges in NoC Design -- 3 NoC Architectures for QoS Support -- 3.1 Connection-Oriented Approach -- 3.2 Connection-Less Approach -- 3.3 Hybrid Techniques -- 4 Fault Tolerance
  • 5 Adaptive Techniques in Real-Time NoCs -- 6 Conclusion -- References -- Cryptography Applications -- Efficient SR-Latch PUF -- 1 Introduction -- 2 Related Work -- 3 Design Methodology -- 4 Bit Generation -- 5 Results -- 5.1 Uniqueness -- 5.2 Reliability -- 5.3 Reliability vs. Error Correction -- 5.4 Entropy Analysis -- 5.5 Cost -- 5.6 Characterization Time -- 6 Conclusion and Future Work -- References -- Hardware Benchmarking of Cryptographic Algorithms Using High-Level Synthesis Tools: The SHA-3 Contest Case Study -- 1 Introduction &amp -- Motivation -- 2 Methodology -- 3 Design -- 3.1 Top-Level Interconnect -- 3.2 Design Techniques -- 4 Results and Discussion -- 4.1 Ranking of Results -- 4.2 Lessons Learned -- 5 Conclusions -- References -- Dual CLEFIA/AES Cipher Core on FPGA -- 1 Introduction -- 2 Considered Ciphers -- 2.1 CLEFIA Algorithm -- 2.2 AES Algorithm -- 3 Related State of the Art -- 3.1 AES Previous Work -- 3.2 CLEFIA Previous Work -- 3.3 Multi-Cryptographic Co-Processors -- 4 Proposed Architecture and Implementation -- 5 Result Analysis -- 6 Conclusion -- References -- Systems and Applications II -- An Efficient and Flexible FPGA Implementation of a Face Detection System -- 1 Introduction -- 2 Background -- 2.1 Cascade Architecture -- 3 Related Work -- 4 Design and Implementation -- 4.1 System Overview -- 4.2 The Evaluator Core -- 4.3 Summary -- 5 Evaluation and Results -- 5.1 Resource Utilization -- 5.2 Performance Comparison -- 5.3 Accuracy Comparison -- 5.4 Comparison with Similar Works -- 5.5 Image Results -- 6 Conclusions -- References -- A Flexible Software Framework for Dynamic Task Allocation on MPSoCs Evaluated in an Automotive Context -- 1 Introduction -- 2 Related Work -- 3 System Architecture -- 4 Structure of the e Software Framework -- 4.1 Data Acquisition -- 4.2 Task Allocation -- 4.3 Transmission via Network-on-Chip
  • 2 A Methodology for Synthesis from Functional EDSLs -- 3 Related Work -- 4 Case Study 1: Matching State of the Art -- 5 Case Study 2: Surpassing State of the Art -- 6 Conclusions and Future Work -- References -- ArchHDL: A Novel Hardware RTL Design Environment in C++ -- 1 Introduction -- 2 A New Hardware Description Environment -- 2.1 Concept of ArchHDL -- 2.2 Hardware RTL Modeling in ArchHDL -- 2.3 Testbench in ArchHDL -- 2.4 Advantages and Disadvantages of ArchHDL over Verilog HDL -- 2.5 Translation Tool from ArchHDL to Verilog HDL -- 3 Experimental Results -- 3.1 A Sample Hardware for Practical Evaluation -- 3.2 Evaluation of Simulation Speed -- 3.3 FPGA Resource Utilization of the Many-core Processor Synthesized from Converted Verilog HDL Code -- 4 Related Works -- 5 Conclusion -- References -- Operand-Value-Based Modeling of Dynamic Energy Consumption of Soft Processors in FPGA -- 1 Introduction -- 2 Related Work -- 3 Operand-Value-Based Processor Energy Model -- 3.1 Base Energy Cost of o Instructions -- 3.2 Maximum Instruct tion Energy Variance -- 3.3 Energy Impact of O Operand Values -- 4 Energy Estimation and Annotation -- 5 Experimental Results -- 5.1 Estimation Accuracy -- 5.2 Estimation Speed -- 6 Conclusion -- References -- Systems and Applications I -- Preemptive Hardware Multitasking in ReconOS -- 1 Introduction -- 2 Related Work -- 3 Methodology: How To Preempt Hardware Tasks -- 3.1 At Task Creation: Parse All Partial Bitstreams -- 3.2 At Task Start: Write Original Bitstream -- 3.3 At Task Preemption: Capture Bitstream -- 3.4 At Task Resumption: Restore Bitstream -- 4 ReconOS Architecture For Hardware Multitasking -- 4.1 ReconOS Multithreading Approach and Architecture -- 4.2 ReconOS ICAP Controller -- 5 Experimental Results -- 6 Conclusion and Future Work -- References -- A Fully Parallel Particle Filter Architecture for FPGAs
  • 1 Introduction -- 2 Architecture Design -- 2.1 FPGA Optimized Resampling -- 3 Implementation -- 4 Evaluation and Results -- 4.1 Simulation of FO-resampling -- 4.2 Performance of FO-resampling on Real Hardware -- 5 Conclusion -- References -- TEAChER: TEach AdvanCEd Reconfigurable Architectures and Tools -- 1 Introduction -- 2 Motivation and Objectives of the TEAChER Project -- 3 The TEAChER Framework -- 4 Development of Educational Material for 3-D Reconfigurable Architectures and CAD Tools -- 5 Virtual Laboratories -- 5.1 Virtual 2D/3D FPGAs -- 5.2 Development of Academic Tools -- 6 Employed Educational and Pedagogical Methods -- 7 Towards Future FPGA Technologies -- 7.1 Teratronics -- 8 Conclusions -- References -- Tools and Compilers II -- Dynamic Memory Management in Vivado-HLS for Scalable Many-Accelerator Architectures -- 1 Introduction -- 2 On the Memory-Induced Resource Under-Utilization in Many-Accelerator FPGAs -- 3 Dynamic Memory Management for Many-Accelerators -- 3.1 Dynamic Memory Management in Vivado-HLS -- 3.2 DMM-HLS Allocation Mechanisms -- 3.3 DMM-HLS Allocation Runtime Issues -- 4 Experimental Results -- 5 Conclusions -- References -- SET-PAR: Place and Route Tools for the Mitigation of Single Event Transients on Flash-Based FPGAs -- 1 Introduction -- 2 Related Works -- 3 The FPGA Logic and Routing Model -- 3.1 Flash-Based FPGA A Modeling -- 4 SET-PAR: Place ement and Routing Tools for SET Mitigatio on -- 4.1 The PDD Placement Algorithm -- 4.2 PDD Routing Algorithm -- 5 Experimental Results -- 6 Conclusions and Future Works -- References -- Advanced SystemC Tracing and Analysis Framework for Extra-Functional Properties -- 1 Introduction -- 2 Goals of this Framework beyond the State-of-the-Art -- 3 Timed Value Streams -- 3.1 Support for Extra-Functional/Physical Quantities -- 3.2 Distributed Time Model and Synchronisation