Uint-Packing: Multiply Your DNN Accelerator Performance via Unsigned Integer DSP Packing

DSP blocks are undoubtedly efficient solutions for implementing multiply-accumulate (MAC) operations on FPGA. Since DSP resources are scarce in FPGA, the advanced solution is to pack parallel multiplication operations into a single DSP. However, available methods are based on signed-type multiplicat...

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Bibliographic Details
Published in2023 60th ACM/IEEE Design Automation Conference (DAC) pp. 1 - 6
Main Authors Zhang, Jingwei, Zhang, Meng, Cao, Xinye, Li, Guoqing
Format Conference Proceeding
LanguageEnglish
Published IEEE 09.07.2023
Subjects
Computational modeling
Design automation
Energy efficiency
Parallel processing
Proposals
Table lookup
Throughput
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DOI10.1109/DAC56929.2023.10247773

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Summary:DSP blocks are undoubtedly efficient solutions for implementing multiply-accumulate (MAC) operations on FPGA. Since DSP resources are scarce in FPGA, the advanced solution is to pack parallel multiplication operations into a single DSP. However, available methods are based on signed-type multiplication, leading to both loss of accuracy and increased area. To solve these issues simultaneously, we propose an unsigned integer DSP packing generalization model called uint-packing. Guided by this generalization model, we design the novel computational structure of the DNN accelerator. Our system design is state-of-the-art, with 2.8× throughput and 4× energy efficiency compared to the third-place DAC-SDC'22 design.
DOI:10.1109/DAC56929.2023.10247773