A Mechanism for Online Diagnosis of Hard Faults in Microprocessors

• Published in: 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'05) pp. 197 - 208
• Main Authors: Bower, Fred A., Sorin, Daniel J., Ozev, Sule
• Format: Conference Proceeding
• Language: English
• Published: Washington, DC, USA IEEE Computer Society 12.11.2005; IEEE
• Series: ACM Conferences
• Subjects: Circuit faults; Costs; Degradation; Electromigration; Error correction; Fault detection; Fault diagnosis; Hardware > Hardware test; Hardware > Integrated circuits; Hardware > Robustness; Microprocessors; Temperature; Wire
• ISBN: 9780769524405; 0769524400
• ISSN: 1072-4451
• DOI: 10.1109/MICRO.2005.8

We develop a microprocessor design that tolerates hard faults, including fabrication defects and in-field faults, by leveraging existing microprocessor redundancy. To do this, we must: detect and correct errors, diagnose hard faults at the field deconfigurable unit (FDU) granularity, and deconfigure FDUs with hard faults. In our reliable microprocessor design, we use DIVA dynamic verification to detect and correct errors. Our new scheme for diagnosing hard faults tracks instructions' core structure occupancy from decode until commit. If a DIVA checker detects an error in an instruction, it increments a small saturating error counter for every FDU used by that instruction, including that DIVA checker. A hard fault in an FDU quickly leads to an above-threshold error counter for that FDU and thus diagnoses the fault. For deconfiguration, we use previously developed schemes for functional units and buffers, and we present a scheme for deconfiguring DIVA checkers. Experimental results show that our reliable microprocessor quickly and accurately diagnoses each hard fault that is injected and continues to function, albeit with somewhat degraded performance.