GPGPU-Accelerated Parallel and Fast Simulation of Thousand-Core Platforms
The multicore revolution and the ever-increasing complexity of computing systems is dramatically changing system design, analysis and programming of computing platforms. Future architectures will feature hundreds to thousands of simple processors and on-chip memories connected through a network-on-c...
Saved in:
Published in | 2011 11th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing pp. 53 - 62 |
---|---|
Main Authors | , , , , , |
Format | Conference Proceeding |
Language | English |
Published |
IEEE
01.05.2011
|
Subjects | |
Online Access | Get full text |
Cover
Loading…
Abstract | The multicore revolution and the ever-increasing complexity of computing systems is dramatically changing system design, analysis and programming of computing platforms. Future architectures will feature hundreds to thousands of simple processors and on-chip memories connected through a network-on-chip. Architectural simulators will remain primary tools for design space exploration, software development and performance evaluation of these massively parallel architectures. However, architectural simulation performance is a serious concern, as virtual platforms and simulation technology are not able to tackle the complexity of thousands of core future scenarios. The main contribution of this paper is the development of a new simulation approach and technology for many core processors which exploit the enormous parallel processing capability of low-cost and widely available General Purpose Graphic Processing Units (GPGPU). The simulation of many-core architectures exhibits indeed a high level of parallelism and is inherently parallelizable, but GPGPU acceleration of architectural simulation requires an in-depth revision of the data structures and functional partitioning traditionally used in parallel simulation. We demonstrate our GPGPU simulator on a target architecture composed by several cores (i.e. ARM ISA based), with instruction and data caches, connected through a Network-on-Chip (NoC). Our experiments confirm the feasibility of our approach. |
---|---|
AbstractList | The multicore revolution and the ever-increasing complexity of computing systems is dramatically changing system design, analysis and programming of computing platforms. Future architectures will feature hundreds to thousands of simple processors and on-chip memories connected through a network-on-chip. Architectural simulators will remain primary tools for design space exploration, software development and performance evaluation of these massively parallel architectures. However, architectural simulation performance is a serious concern, as virtual platforms and simulation technology are not able to tackle the complexity of thousands of core future scenarios. The main contribution of this paper is the development of a new simulation approach and technology for many core processors which exploit the enormous parallel processing capability of low-cost and widely available General Purpose Graphic Processing Units (GPGPU). The simulation of many-core architectures exhibits indeed a high level of parallelism and is inherently parallelizable, but GPGPU acceleration of architectural simulation requires an in-depth revision of the data structures and functional partitioning traditionally used in parallel simulation. We demonstrate our GPGPU simulator on a target architecture composed by several cores (i.e. ARM ISA based), with instruction and data caches, connected through a Network-on-Chip (NoC). Our experiments confirm the feasibility of our approach. |
Author | Benini, L. Pinto, C. Raghav, S. Ruggiero, M. Marongiu, A. Atienza, D. |
Author_xml | – sequence: 1 givenname: C. surname: Pinto fullname: Pinto, C. organization: DEIS, Univ. of Bologna, Bologna, Italy – sequence: 2 givenname: S. surname: Raghav fullname: Raghav, S. organization: ESL - EPFL, Lausanne, Switzerland – sequence: 3 givenname: A. surname: Marongiu fullname: Marongiu, A. organization: DEIS, Univ. of Bologna, Bologna, Italy – sequence: 4 givenname: M. surname: Ruggiero fullname: Ruggiero, M. organization: DEIS, Univ. of Bologna, Bologna, Italy – sequence: 5 givenname: D. surname: Atienza fullname: Atienza, D. organization: ESL - EPFL, Lausanne, Switzerland – sequence: 6 givenname: L. surname: Benini fullname: Benini, L. organization: DEIS, Univ. of Bologna, Bologna, Italy |
BookMark | eNotzMtKw0AUgOERFbQ1Wzdu5gUSM5czl2UJNhYKBmzX5WQuGEgTmUkXvr0FXf2LD_4VuZvmKRDyzOqKsdq-Nk2bBl_xmrFKyRtSWG1qrSxIYUHdkhWToHXNuJUPpMh56GuutAIN9pHs2q7tjuXGuTCGhEvwtMOE4xhGipOnW8wL_RzOlxGXYZ7oHOnha77kq5XNnALtrhDndM5P5D7imEPx3zU5bt8OzXu5_2h3zWZfIldKltpL55iKKBUacJpbpY0VjgPnEWKvUUsGfYy9cYAgPThjnTJCCOddsGJNXv6-Qwjh9J2GM6afE1hpwCrxCylOTsw |
ContentType | Conference Proceeding |
DBID | 6IE 6IL CBEJK RIE RIL |
DOI | 10.1109/CCGrid.2011.64 |
DatabaseName | IEEE Electronic Library (IEL) Conference Proceedings IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume IEEE Xplore All Conference Proceedings IEEE Xplore IEEE Proceedings Order Plans (POP All) 1998-Present |
DatabaseTitleList | |
Database_xml | – sequence: 1 dbid: RIE name: IEEE Xplore url: https://proxy.k.utb.cz/login?url=https://ieeexplore.ieee.org/ sourceTypes: Publisher |
DeliveryMethod | fulltext_linktorsrc |
EISBN | 9780769543956 0769543952 |
EndPage | 62 |
ExternalDocumentID | 5948596 |
Genre | orig-research |
GroupedDBID | 6IE 6IF 6IK 6IL 6IN AAJGR ALMA_UNASSIGNED_HOLDINGS BEFXN BFFAM BGNUA BKEBE BPEOZ CBEJK IEGSK IERZE OCL RIE RIL |
ID | FETCH-LOGICAL-a2664-7d4cc16fa46a85c72967893c2522f5fb7a7415bffb8c5a54d5c89c68333cdce93 |
IEDL.DBID | RIE |
ISBN | 1457701294 9781457701290 |
IngestDate | Wed Jun 26 19:20:17 EDT 2024 |
IsDoiOpenAccess | false |
IsOpenAccess | true |
IsPeerReviewed | false |
IsScholarly | false |
Language | English |
LinkModel | DirectLink |
MergedId | FETCHMERGED-LOGICAL-a2664-7d4cc16fa46a85c72967893c2522f5fb7a7415bffb8c5a54d5c89c68333cdce93 |
OpenAccessLink | https://infoscience.epfl.ch/record/164471/files/CCGRID2011-pinto_et_al.pdf |
PageCount | 10 |
ParticipantIDs | ieee_primary_5948596 |
PublicationCentury | 2000 |
PublicationDate | 2011-05 |
PublicationDateYYYYMMDD | 2011-05-01 |
PublicationDate_xml | – month: 05 year: 2011 text: 2011-05 |
PublicationDecade | 2010 |
PublicationTitle | 2011 11th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing |
PublicationTitleAbbrev | ccgrid |
PublicationYear | 2011 |
Publisher | IEEE |
Publisher_xml | – name: IEEE |
SSID | ssib026765759 ssib040743469 ssj0000668891 |
Score | 1.5647893 |
Snippet | The multicore revolution and the ever-increasing complexity of computing systems is dramatically changing system design, analysis and programming of computing... |
SourceID | ieee |
SourceType | Publisher |
StartPage | 53 |
SubjectTerms | Computational modeling Computer architecture CUDA GPGPU Graphics processing unit Hardware ISS manycore NoC Programming simulation Switches |
Title | GPGPU-Accelerated Parallel and Fast Simulation of Thousand-Core Platforms |
URI | https://ieeexplore.ieee.org/document/5948596 |
hasFullText | 1 |
inHoldings | 1 |
isFullTextHit | |
isPrint | |
link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwjV09T8MwELVKJyZALeJbHhhxmw_bsUcU0Rakoki0UrfKOduiAlLUpgu_HjtJS4UY2PIxJLlYfufzvfcQug0S0CakhlhtYkLdgoBIC4zkIjSRW_gIC57vPH7moyl9mrFZC93tuDDGmKr5zPT8YbWXr5ew8aWyvpcWYZIfoAMRRDVXazt2Ip5wtiddRz000to8u5mVuRAyrLhdLEl8_YVuJZ-a86ARdQwD2U_T4Wqha4lPr0awZ71SIc_gCI2371w3nLz1NmXeg69fco7__ahj1P3h-OFsh14nqGWKDnocZsNsSu4BHBp5EQmNM7XydivvWBUaD9S6xC-Lj8bzCy8tnrwufWOPJql7MM7cDZ8Gr7toOniYpCPSmC0Q5TCakkRTgJBbRbkSDFzO7WBMxuB-WGSZzRPlc4_c2lwAU4xqBkICF3EcgwYj41PULpaFOUOY-3kkoTI2RlIbgbQarBcK1C6alopz1PFhmH_WehrzJgIXf1--RId1Hdc3GV6hdrnamGuXCJT5TTUCvgHjIKuw |
link.rule.ids | 310,311,786,790,795,796,802,27956,55107 |
linkProvider | IEEE |
linkToHtml | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwjV3PT8IwFG4QD3pSA8bf9uDRwsbarj0aIj8UyBIh4Ua21zYSdRgYF_96220gMR687cdh21vT7_X1fd-H0J0XgtI-1cQoHRBqFwREGmAkEb5u2YWPMOD4zsMR703o05RNK-h-y4XRWufNZ7rhDvO9fLWAtSuVNZ20CJN8D-1bnPfCgq21GT0tHnK2I15HHTjSwj67nJe5ENLP2V0sDF0Fhm5En8pzr5R19D3ZbLe7y7kqRD6dHsGO-UqOPZ0jNNy8ddFy8tZYZ0kDvn4JOv73s45R_Yflh6Mtfp2gik5rqN-NutGEPABYPHIyEgpH8dIZrrzjOFW4E68y_DL_KF2_8MLg8evCtfYo0rYPxpG94RLhVR1NOo_jdo-UdgsktihNSagogM9NTHksGNis2wKZDMD-spZhJgljl30kxiQCWMyoYiAkcBEEASjQMjhF1XSR6jOEuZtJQioDrSU1LZBGgXFSgcpG01BxjmouDLPPQlFjVkbg4u_Lt-igNx4OZoP-6PkSHRZVXddyeIWq2XKtr21akCU3-Wj4BigTrwQ |
openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=2011+11th+IEEE%2FACM+International+Symposium+on+Cluster%2C+Cloud+and+Grid+Computing&rft.atitle=GPGPU-Accelerated+Parallel+and+Fast+Simulation+of+Thousand-Core+Platforms&rft.au=Pinto%2C+C.&rft.au=Raghav%2C+S.&rft.au=Marongiu%2C+A.&rft.au=Ruggiero%2C+M.&rft.date=2011-05-01&rft.pub=IEEE&rft.isbn=9781457701290&rft.spage=53&rft.epage=62&rft_id=info:doi/10.1109%2FCCGrid.2011.64&rft.externalDocID=5948596 |
thumbnail_l | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=9781457701290/lc.gif&client=summon&freeimage=true |
thumbnail_m | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=9781457701290/mc.gif&client=summon&freeimage=true |
thumbnail_s | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=9781457701290/sc.gif&client=summon&freeimage=true |