STRAIGHT hazardless processor architecture without register renaming
The single-thread performance of a processor improves the capability of the entire system by reducing the critical path latency of programs. Typically, conventional superscalar processors improve this performance by introducing out-of-order (OoO) execution with register renaming. However, it is also...
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Published in | 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) pp. 121 - 133 |
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Main Authors | , , , , , , , , , , |
Format | Conference Proceeding |
Language | English |
Published |
Piscataway, NJ, USA
IEEE Press
20.10.2018
IEEE |
Series | ACM Conferences |
Subjects | |
Online Access | Get full text |
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