STRAIGHT hazardless processor architecture without register renaming

The single-thread performance of a processor improves the capability of the entire system by reducing the critical path latency of programs. Typically, conventional superscalar processors improve this performance by introducing out-of-order (OoO) execution with register renaming. However, it is also...

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Bibliographic Details
Published in2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) pp. 121 - 133
Main Authors Irie, Hidetsugu, Koizumi, Toru, Fukuda, Akifumi, Akaki, Seiya, Nakae, Satoshi, Bessho, Yutaro, Shioya, Ryota, Notsu, Takahiro, Yoda, Katsuhiro, Ishihara, Teruo, Sakai, Shuichi
Format Conference Proceeding
LanguageEnglish
Published Piscataway, NJ, USA IEEE Press 20.10.2018
IEEE
SeriesACM Conferences
Subjects
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