STRAIGHT hazardless processor architecture without register renaming

• Published in: 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) pp. 121 - 133
• Main Authors: Irie, Hidetsugu, Koizumi, Toru, Fukuda, Akifumi, Akaki, Seiya, Nakae, Satoshi, Bessho, Yutaro, Shioya, Ryota, Notsu, Takahiro, Yoda, Katsuhiro, Ishihara, Teruo, Sakai, Shuichi
• Format: Conference Proceeding
• Language: English
• Published: Piscataway, NJ, USA IEEE Press 20.10.2018; IEEE
• Series: ACM Conferences
• Subjects: compiler; Computer architecture; Computer systems organization; Computer systems organization > Dependable and fault-tolerant systems and networks; General and reference; General and reference > Cross-computing tools and techniques; General and reference > Cross-computing tools and techniques > Performance; Hardware; Instruction sets; instruction-level-parallelism; Microarchitecture; microprocessor; Networks; Networks > Network performance evaluation; out-of-order execution; Pipelines; power efficiency; register renaming; Registers; Scalability; Social and professional topics; Social and professional topics > Professional topics; Social and professional topics > Professional topics > Computing profession; Social and professional topics > Professional topics > Computing profession > Testing, certification and licensing; Software and its engineering; Software and its engineering > Software notations and tools; Software and its engineering > Software notations and tools > Compilers; microprocessor; out-of-order execution; computer architecture; instruction-level-parallelism; register renaming; compiler; power efficiency
• DOI: 10.1109/MICRO.2018.00019
• ISBN: 9781538662403; 153866240X

The single-thread performance of a processor improves the capability of the entire system by reducing the critical path latency of programs. Typically, conventional superscalar processors improve this performance by introducing out-of-order (OoO) execution with register renaming. However, it is also known to increase the complexity and affect the power efficiency. This paper realizes a novel computer architecture called "STRAIGHT" to resolve this dilemma. The key feature is a unique instruction format in which the source operand is given based on the distance from the producer instruction. By leveraging this format, register renaming is completely removed from the pipeline. This paper presents the practical Instruction Set Architecture (ISA) design, the novel efficient OoO microarchitecture, and the compilation algorithm for the STRAIGHT machine code. Because the ISA has sequential execution semantics, as in general CPUs, and is provided with a compiler, programming for the architecture is as easy as that of conventional CPUs. A compiler, an assembler, a linker, and a cycle-accurate simulator are developed to measure the performance. Moreover, an RTL description of STRAIGHT is developed to estimate the power reduction. The evaluation using standard benchmarks shows that the performance of STRAIGHT is 18.8% better than the conventional superscalar processor of the same issue-width and instruction window size. This improvement is achieved by STRAIGHT's rapid miss-recovery. Compilation technology for resolving the possible overhead of the ISA is also revealed. The RTL power analysis shows that the architecture reduces the power consumption by removing the power for renaming. The revealed performance and efficiencies support that STRAIGHT is a novel viable alternative for designing general purpose OoO processors.