DNNBuilder: an Automated Tool for Building High-Performance DNN Hardware Accelerators for FPGAs

• Published in: 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) pp. 1 - 8
• Main Authors: Zhang, Xiaofan, Wang, Junsong, Zhu, Chao, Lin, Yonghua, Xiong, Jinjun, Hwu, Wen-mei, Chen, Deming
• Format: Conference Proceeding
• Language: English
• Published: ACM 01.11.2018
• Subjects: Field programmable gate arrays; Memory management; Pipelines; Resource management; System-on-chip; Throughput

Building a high-performance FPGA accelerator for Deep Neural Networks (DNNs) often requires RTL programming, hardware verification, and precise resource allocation, all of which can be time-consuming and challenging to perform even for seasoned FPGA developers. To bridge the gap between fast DNN con...