Thermal signature a simple yet accurate thermal index for floorplan optimization

• Published in: 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC) pp. 108 - 113
• Main Authors: Kung, Jaeha, Han, Inhak, Sapatnekar, Sachin, Shin, Youngsoo
• Format: Conference Proceeding
• Language: English
• Published: New York, NY, USA ACM 05.06.2011; IEEE
• Series: ACM Conferences
• Subjects: Accuracy; Correlation; Hardware > Electronic design automation > Logic synthesis > Circuit optimization; Hardware > Very large scale integration design; Heating; Runtime; Simulated annealing; Thermal analysis; thermal-aware floorplanning; thermal-aware floorplanning; thermal analysis
• ISBN: 1450306365; 9781450306362
• ISSN: 0738-100X
• DOI: 10.1145/2024724.2024748

A floorplanning has a potential to reduce chip temperature due to the conductive nature of heat. If floorplan optimization, which is usually based on simulated annealing, is employed to reduce temperature, its evaluation should be done extremely fast with high accuracy. A new thermal index, named thermal signature, is proposed. It approximates the temperature calculation, which is done by taking the product of Green's function and power density integrated over space. The correlation coefficient between thermal signature and temperature is shown to be quite high, more than 0.7 in many examples. A floorplanner that uses thermal signature is constructed and assessed using real design examples in 32-nm technology. It produces a floorplan whose maximum temperature is 11.4°C smaller than that of standard floorplan, on average, in reasonable amount of runtime.