POWER7 - Verification challenge of a multi-core processor

• Published in: 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers pp. 809 - 812
• Main Author: Schubert, K.-D.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.11.2009
• Subjects: Energy management; Formal verification; Hardware; Hardware Acceleration; Life estimation; Microprocessors; Multicore processing; Permission; Sequential analysis; Simulation; Structural Checking; Test Generation; Testing; Yarn
• ISSN: 1092-3152
• DOI: 10.1145/1687399.1687551

Over the years functional hardware verification has made significant progress in the areas of traditional simulation techniques, hardware accelerator usage and last but not least formal verification approaches. This has been sufficient to deal with the additional design content and complexity increase that has been happening at the same time. For POWER7, IBM's first high end 8-core microprocessor, these incremental improvements in verification have been deemed not to be enough by themselves, because the chip was not just a remap of an existing design with more cores. The infrastructure on the chip had to be changed significantly, while at the same time the business side requested a shorter development cycle with perfect quality but without growing the team. Looking at these constraints a two phase approach seemed to be the only solution. This paper commences with the highlights of the first phase, where improvements to the existing process have been identified. This includes topics ranging from enhanced test case generation, over advancements in structural checking to the extensions of the formal verification scope both in property checking and sequential equivalence checking. At the same time, the paper describes the second phase which has targeted the exploitation of synergy across the various verification activities. The active interlock between simulation, formal verification and the design has helped to reduce workload and improved the project schedule. And the usage of coverage in holistic way from unit level simulation to acceleration has led to new innovations and new insight, which improved the overall verification process. Finally, an outlook on future challenges and future trends is given. Categories and Subject Descriptors B.6.3 [Logic Design]: Design Aids - Verification. General Terms Verification