Joint design-time and post-silicon optimization for digitally tuned analog circuits

• Published in: 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers pp. 725 - 730
• Main Authors: Wei Yao, Yiyu Shi, Lei He, Pamarti, S.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.11.2009
• Subjects: Analog circuits; Capacitance; Circuit optimization; Constraint optimization; Design optimization; Optimization methods; Phase locked loops; Space exploration; Transmitters; Tunable circuits and devices

Joint design time and post-silicon optimization for analog circuits has been an open problem in literature because of the complex nature of analog circuit modeling and optimization. In this paper we formulate the co-optimization problem for digitally tuned analog circuits to optimize the parametric...